VERILOG-A

HOW TO EXECUTE VERILOG-A FILE IN CADENCE VIRTUOSO TOOL

What is Verilog-A?

Verilog-A is a more advanced form of analog behavioural modelling as implemented in most SPICE programs by an arbitrary source. But whereas an arbitrary source can implement only a single static equation, Verilog-A provides a complete language with advanced features such as looping, events, conditional statements, arrays and much more. Further, because Verilog-A is compiled to binary, the resulting model is fast and efficient.
Verilog-A has a wide variety of applications. Examples include, semiconductor devices, behavioural models, electromechanical systems, DSP functions and A-D and D-A conversion. It is even possible to implement digital functions with Verilog-A and for simple devices this is sometimes more efficient than a digital implementation as there is no need for A-D interfaces.

Key features
    * Supplied with fully integrated open-source Verilog simulators
    * Also possible to use third party Verilog simulators with Mentor Graphics Modelsim fully supported
    * Verilog-A analog modelling language compiler

Who's it for?
    * Engineers who want to extend their circuit simulators to use the industry standard Verilog hardware description language.
    * Engineers who need sophisticated high-performance analog models 

How to Start

 The software will be install in the root plate form 
Open Terminal

  Type "cd cadence"  (press Enter)
          "csh"  (press Enter)
          "source cshrc" (press Enter)
After pressing enter a message "welcome to  cadence tools" will be display
         "cd Database"  (press Enter)
        "cd cadence" (and press tab)  cd cadence _analog_Labs_613 will display then press Enter and at last type
         "virtuoso" (press Enter)

this is also shown by figure below

When you press enter after  command "virtuoso"  A CDS. log window ( it also called Main window ) will open  

Example INVERTER:

Now we take an example of Inverter for more knowledge about this tool
here new Library name is "Usmani" and new Cell name is "Inverter" 

Building Blocks of an Inverter:

  1) Create own Library and Cell
  2) Symbol Creation

  3) Write Verilog-A model 
  4) Building the Inverter_Test Design
  5) Analog Simulation with Spectre

1) Create own Library and Cell

In the CDS.log window or Main window goto "File >New >Library" as show given figure

 When you click on Library a new window will open for creating new Library name, I already mentioned you, my library name is "Usmani_VerilogA" so you will write "Usmani_VerilogA" in the Library name column, and this library will attach to an existing technology library   also shown by figure 

after creating new library name "Usmani_VerilogA" and it attached by existing library click on "OK"  a new window will open like below, here you will choose any one existing technology library  suppose here we choose "gpdk180" then click "OK"

Click"OK", Now you can see in the CDS.log window or Main window a new message "Successfully attached to an existing technology library  gpdk180 " will display

Now you have to create new "Cellview" , so go to the CDS.log window or Main window and then go to the File>New>Cellvie, such as 

a new window will open  

library .............Usmani_VerilogA 

Cell ..................Inverter

View ................Schematic 

Type ................SchematicSymbol

Open with........Symbol L

this is also shown by below figure 

when you will click "Ok" a new blank black window will open such as

In this section we create the symbol of a  inverter to look like a Inverter gate symbol.

1. Execute "Create > Shape > polygon", and draw a shape similar to triangle.

2. After creating the triangle press ESC key.

3. Execute "Create > Shape > Circle" to make a circle at the end of triangle.

4. You can move the pin names according to the location.

5. Execute "Create > Selection Box" . In the Add Selection Box form, click Automatic.

A new red selection box is automatically added.

6. After creating symbol, click on the save icon in the symbol editor window to save the symbol. In the symbol editor, execute "File > Close" to close the symbol view window.

   

Click the Check and Save icon in the schematic editor window.

Observe the CIW output area for any errors.

  In this section, you will write a Verilog-A code for a inverter design so you can place it in a test circuit for simulation. A symbol view is extremely important step in the design process. The symbol view must exist for the schematic to be used in a hierarchy. In addition, 1. In the Inverter schematic window, execute
  

Goto 

Create > Cellview > From Cellview.

a new window will pop-up and set it as given below

Library Name.....................Usmani_VerilogA

Cell Name     ..................... Inverter

From View Name ............... Symbol

To view Name .................. Schematic

Tool/Data Type ................ VerilogA-Editor 

after click OK a Text file will open 

Write Verilog-A Model of a Inverter and save it.  

4) Building the Inverter_Test Design  

                                                                                                                             

Open new Inverter_Test window

1. In the CIW or Library Manager, execute" File > New > Cellview "

2. Set up Usmani_VerilogA in Library column and Inverter_Test in Cell column the New File form as follows  

3. Click "OK" when done. A blank schematic window for the Inverter_Test design appears.

Building the Inverter_Test Circuit

1.Click "Adding fixed menu Icon > browse "  a Library manager will open now choose library name, cell name and Properties as given below in the table  and build the build the Inverter_Test schematic.

Library name	Cellview name	Properties/Comments
Usmani	Inverter	Symbol
analogLib	Vpulse	v1=0, v2=1.8,td=0 tr=tf=1ns, ton=10n, T=20n
analogLib	gnd

Note: Remember to set the values for VDD and VSS. Otherwise, your circuit will have no power.

2. Add the above components using "Create > Instance" or by pressing "I". or  click on this icon

3. Click the " Wire (narrow)" icon and wire your schematic.     

 Tip: You can also press the w key, or execute" Create > Wire (narrow)."

4.  Click "Create  > Wire Name" or press "L" to name the input (Vin) and output (Vout) wires as in the below schematic. 
5. Click on the "Check and Save" icon to save the design.  

6. The schematic should look like this.

7. Leave your Inverter_Test schematic window open for the next section.

5)  Analog Simulation with Spectre

Objective: To set up and run simulations on the Inverter_Test design

In this section, we will run the simulation for Inverter and plot the transient, DC characteristics and we will do Parametric Analysis after the initial simulation.

Starting the Simulation Environment

Start the Simulation Environment to run a simulation.

1. In the Inverter_Test schematic window, execute  "Launch  > ADE L"

The Virtuoso Analog Design Environment (ADE) simulation window appears.

Choosing a Simulator

Set the environment to use the Spectre® tool, a high speed, highly accurate

analog simulator. Use this simulator with the Inverter_Test design, which is made-up of analog components.

1. In the simulation window (ADE), execute

"Setup >  Simulator/Directory/Host".

2. In the Choosing Simulator form, set the Simulator field to spectre (Not spectreS) & click "OK"

Setting the Model Libraries

The Model Library file contains the model files that describe the nmos and pmos devices

during simulation.

1.  In the simulation window (ADE),

Execute Setup  > Model Libraries.

The Model Library Setup form appears. Click the browse button to add gpdk.scs if not added by default as shown in the Model Library Setup form.

Remember to select the section type as stat in front of the gpdk.scs file.

Your Model Library Setup window should now looks like the below figure.

    
To view the model file, highlight the expression in the Model Library File field and Click Edit File.         

                                                                  
2. To complete the Model Library Setup, move the cursor and click "OK".

The Model Library Setup allows you to include multiple model files.

It also allows you to use the Edit button to view the model file.

Choosing Analyses

This section demonstrates how to view and select the different types of analyses to complete the circuit when running the simulation.

1. In the Simulation window (ADE L), click the Choose > Analyses icon.   

You can also execute Analyses > Choose.                       

The Choosing Analysis form appears. This is a dynamic form, the bottom of the form

changes based on the selection above.

2. To setup for transient analysis

          a. In the Analysis section select "tran"

          b. Set the stop time as 200n

          c. Click at the moderate or Enabled button at the bottom, and then click "Apply".

                        

3. To set up for DC Analyses:

        

          a. In the Analyses section, select "dc".

          b. In the DC Analyses section, turn on Save DC Operating Point.

          c. Turn on the Component Parameter.
          d. Double click the Select Component, after double click cursor will goes to Test schematic       

          e. Click input signal vpulse source in the test schematic window. 
               a new window will popup 

          f. Click “DC Voltage” in the Select Component Parameter form and click OK.

          f. In the analysis form type start and stop voltages as 0 to 1.8 respectively.

          g. Check the enable button and then click Apply.

4. Click "OK" in the Choosing Analyses Form.

Selecting Outputs for Plotting

1. Execute "Outputs  > To be plotted > Select on Schematic" in the simulation window.

2. Follow the prompt at the bottom of the schematic window, Click on output

net Vout, input net Vin of the Inverter. Press ESC with the cursor in the schematic after selecting it.

Does the simulation window look like this?

 

Running the Simulation

1. Execute Simulation > Netlist and Run in the simulation window to start the  

Simulation or the icon, this will create the netlist as well as run the simulation.

2. When simulation finishes, the Transient, DC plots automatically will be popped up along with log file.